1. Field
This disclosure relates generally to integrated circuits and their fabrication and, more particularly, to integrated circuit devices having through-silicon vias.
2. Description of the Related Art
To facilitate on-going trends in electronics for faster, more powerful, and denser integrated circuit devices, three dimensional (3-D) integration or packaging technology has been developed. Three-dimensional integration refers to the vertical stacking of multiple dies or wafers, each including integrated circuits (ICs), within a package. Holes or vias (known as “through-silicon vias”, or “TSVs”) extending through one or more wafers can contain conductive material such as copper and can be aligned when the wafers are stacked to provide electrical communication among the ICs in the stacked wafers. Thus, multiple wafers can be electrically connected using vertical-extending conductive structures formed in the vias.
In some other applications, the TSVs can also serve as a low inductance and low resistance connection among ICs in the stacked wafers or to a global ground plane.
Because the TSVs can be significantly larger than other features in an IC, formation of TSVs and the structures contacted by them can present particular challenges.